Electric dynamically operated storage element

ABSTRACT

An electric dynamically operated storage element comprises two energy stores. Each store has a charging circuit including a rectifying element and a discharging circuit including a controlled respectively variable resistance connected in series with the rectifying element. Also, circuitry is provided for applying periodically repeating phase clock pulses simultaneously to the energy stores through the charging circuits.

United States Patent [1 1 Haraszti 1451 Aug. 14, 1973 ELECTRIC DYNAMICALLY OPERATED STORAGE ELEMENT [75] Inventor: Tegze Haraszti,1-1eilbronn, Germany [73] Assignee: Lincentia Patent-Verwaltungs- GmbH Frankfurt am Main,

sm [22] Filed: Aug. 10, 1971 21 Appl. No.: 170,509

[30] Foreign Application Priority Data Aug. 10, 1970 Germany P 20 39 606.9

Aug. 10, 1970 Germany P 70 29 971.7

[52] US. Cl 307/279, 307/208, 307/238, 307/304, 307/303 [51] Int. Cl. "03k 3/286 [58] Field of Search 307/238, 279, 304, 307/303 [56] References Cited UNITED STATES PATENTS 3,639,787 2/1972 Lee ..307/304 3,390,382 6/1968 lgarashi ..307/238 X 3,514,765 5/1970 Christensen ..307/279 X 3,530,443 9/1970 Crafts et a1 ..307/279 X 3,564,300 2/1971 Henle .307/238 X Primary Examiner-John S. Heym an Attorney-Spencer & Kaye giiensslen H ,307/279 [57] ABSTRACT 15 Claims, 10 Drawing Figures ELECTRIC DYNAMICALLY OPERATED STORAGE ELEMENT BACKGROUND OF THE INVENTION The invention relates to an electric, dynamically operated storage element of two controllable resistors and at least two energy stores of which each is associated with a charging and a discharging circuit.

An electric storage element has already been proposed which consists of at least two controllable circuit elements which are in opposite phase in the conducting and blocked states respectively, irrespective of the state of charge of two capacitances in parallel to their control electrodes. A charging and a discharging circuit is provided for each capacitance. Through these circuits, the capacitances are charged by different phase clock pulses, offset in time relative to each other, and then again discharged in accordance with their original state of charge, or left in the charged state. Such a storage element is also called a 4-pulse storage element because four cyclically repeating clock pulses are necessary for maintaining the stored data. Such storage elements which are operated dynamically, contrary to known statically operated storage elements, are characterized by the high speed with which data can be read out and stored. In addition, the power consumption of the storage element is very low. This is due to the fact that the storage element consuming power only during the recharging or charging of the store capacitance.

In the previous proposed storage element, it is regarded as a disadvantage that a four-pulse generator is necessary for operating the storage element which supplies the clock pulses with the mutual phasing. Since the different clock pulses are also supplied to dif ferent points of the circuit, clock lines must be provided which require much space, particularly in integrated semiconductor circuits and are technologically expensive. In the older proposal of a storage element, six field effect transistors are provided for the circuit, and it is desirable to reduce the number of circuit elements used.

SUMMARY OF THE INVENTION The object of the invention is to provide a storage element which consists of as few circuit elements as pos sible and may be operated as simply as possible.

According to the invention there is provided an elec tric dynamically operated storage element comprising two energy stores, a charging circuit for each said energy store comprising a rectifying element, a discharging circuit for each said energy store comprising a variable resistor connected in series with the associated rectifying element and means for applying periodically repeating phase clock pulses through said charging circuits simultaneously to said energy stores.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in greater detail, by way of example, with reference to the accompanying drawings, in which:

FIG. I shows the basic circuit diagram of the storage element according to the invention; r

FIG. 2 shows the tirne-voltage diagram of the phase clock pulse and the voltage across the input or output. electrode, respectively, for a defined state of the store;

FIG. 3 shows the non-linearity of the variable resistors;

FIG. 4 shows the resistance behavior of the two variable resistors during the duration of a phase clock pulse;

FIG. 5 shows the capacitance voltage behavior of the energy stores where these are intrinsic capacitances;

FIG. 6 shows the associated voltage ratio at the input and at the output electrode of the circuit during a phase clock pulse;

FIG. 7 shows the capacity-voltage diagram of another non-linear capacitance;

FIGS. 8 and 9 show two different possibilities for realizing the storage element according to the invention; and

FIG. 10 shows the storage cell in the form of an integrated solid state unit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a storage element having two variable resistors and two energy stores with each of which is associated a charging and discharging circuit, it is proposed that the charging circuit of each energy store consists of a rectifying element, connected in series with a controllable resistance forming a discharge circuit, wherein both energy stores are connected through the charging circuits simultaneously to periodically repeating phase clock pulses and the non-linearity of the elements and the duration of the phase clock pulses is so chosen that the stored data is renewed with each phase clock pulse, or replaced by the negated data.

This storage element can have the great advantage that it can be operated with a single, periodically repeated phase clock pulse. For this reason, the storage element can quickly store and release data. The power absorption is small. Technical expenditure has been much reduced because only a single phase clock line is necessary. As will be shown in detail, in the following description, a plurality of storage. elements may be housed in a single semiconductor body, wherein all storage elements receive the clock pulse simultaneously through the semiconductor body. In this case, a separate clock line is completely eliminated because it is only necessary to connect the semiconductor body to the clock generator for the phase clock pulses. As will also be shown in the following description, the storage element accordingto the invention may be realized with an extremely small number of circuit elements. Thus, for example, a storage element may consist of only two field effect transistors, the electrodes of which are interconnected in a suitable manner. The space requirements of such a storage element on a semiconductor substrate are very small. The manufacture of a complex store using the arrangement according to the invention is simple and cheap.

The operation of storage elements: according to the invention, is based on the fact that with the use of nonlinear components, the energy stores do not discharge uniformly and quickly with the start of a phase clock pulse. The discharging times are a function of the energy content of the store prior to the start of the phase clock pulse.

In the storage element according to the invention, the energy stores consist preferably of capacitances, connected in parallel to the controllable resistances or in parallel to the rectifying components. These capacitances may be fixed capacitances or the inherent capacitances of the used controllable resistances and of the rectifying elements. The controllable resistances are preferably MIS or MOS field effect transistors, the control electrodes of which are insulated from the semiconductor body. In this case, the capacitances consist of the input capacitance of one transistor, a bar rier layer capacitance of the other transistor, and possibly of the barrier layer capacitance of the rectifying component. With the applied voltage these capacitors exhibit a non-linear behavior.

The rectifying components are preferably diodes. In a preferred embodiment of field effect transistors, they are realized by the barrier layer between a main electrode and the semiconductor body. The main electrodes are the source and drain electrodes of the MIS or MOS field effect transistor.

In order to obtain a data stored in the storage element, the non-linearity of the controllable resistances and the duration of the phase clock pulses must be such that the resistance, changed by the stored data into a low-value, remains smaller during the duration of the phase clock pulses than the resistance changed from a high-value to a low value state only after the start of the phase clock pulse.

The writing in of a data is effected simply in such a way that one or both storage capacitances are brought into a certain state of charge in accordance with the data to be stored. Here, for example, the voltage corresponds to a logic 0, while a negative voltage of a certain magnitude corresponds to a logic 1.

Referring now to the drawings, in FIG. 1 the storage element consists of two variable resistances R and R Each resistance is connected in series to a circuit element G, and G, with rectifying properties. The rectifier must be so connected in series to a variable resistance that at the start of a phase clock pulse, the rectifiers become conducting. The junction between the series circuit of a rectifier and one variable resistance is connected to the control electrode of the other variable resistance. Thus, in the circuit of FIG. 1 the junction acts between G, and R is connected to the control electrode of R and the junction Y between G and R is connected to the control electrode of R,,,. A capacitance C, and C, respectively is connected in parallel to R,,, and R,,,. The free electrodes of the rectifiers G, and G, are interconnected andv are connected through the point A to the clock generator for the phase clock pulse (ii. The free electrodes of the variable resistances are grounded or also connected to the point A.

Let it first be assumed that the capacitances C, and C are linear. At the circuit point B which is identical with x, there is a negative potential, i.e., a logic I; at the circuit point F identical with y, there is 0 voltage, i.e., a logical 0. This is the state of store of the element which has been inscribed and which should now be maintained by means ofa phase clock pulse. For realizing a logic I, a negative voltage will be used if the storage element is realized by the circuits according to FIGS. 8 to 10. In these embodiments MOS field effect transistors Q, and Q, with p channel enhancement are used. These transistors have a low resistance when a negative potential is applied at the control electrode, and a voltage is applied between the main electrodes, but have a high resistance or are blocked with O voltage at the control electrode.

Assuming these conditions, the resistance R is low owing to the negative potential at x. The resistance of R is substantially constant for the duration of the phase clock pulse and low ohmic, as shown in FIG. 4. The capacitance C, is charged to the voltage U. This state of charge is shown in the bottom graph in FIG. 2. FIG. 2 also shows the curve of the phase clock pulses and of the voltage at the point F as a function of the time. With the start of the phase clock pulse (1) at the point A, the diode D (FIGS. 8 and 9) becomes conducting and the capacitance C, charges with a certain time constant, as shown in the center graph in FIG. 2. In consequence of the rising voltage at the point F, the voltage at the control electrode of the resistance R, becomes larger, and the resistance therefore become smaller. FIG. 4 shows how the value of the resistor R,,, drops with rising voltage at the point F from a high resistance value to a low resistance value during the duration T of the phase clock pulse. The phase clock pulse is so timed that the resistor R,,, is, at the end of the phase clock pulse, above the value of the resistor R by an amount A R. The same behavior is also obtained if the voltage at F has reached the maximum voltage value U already before the end of the phase clock pulse, as indicated in FIG. 2. This is due to the fact that the reduction of the resistance is delayed by the nonlinearity and by physical processes. This is valid to a special degree for MOS field effect transistors Q, and 0,, such as are used in the embodiments of FIGS. 8 and 9.

The operation of the arrangement according to the invention is particularly good with extremely short phase clock pulses, but it has been shown by tests that the storage element retains the stored data content even with phase clock pulses clock pulses of several microseconds duration.

At the moment when the difference between the two resistance values R, and R is still large enough, the phase clock pulse 4) stops suddenly and the voltage at the point A becomes 0. The diodes D, and D (FIGS. 8 and 9) are therefore operated in the blocking direction. The capacitance C, can now discharge only through R, and the capacitance C, only through R Since at this moment the resistance value R is smaller than R,,,, C, can discharge more quickly 'than C,. In consequence the voltage at F drops more quickly than at E, so that the control voltage at the control electrode of the resistor R drops more quickly than the voltage at the control electrode of R,,,. In consequence, the resistance of R, increases more quickly than that of R,,,. The differential drop in the voltages and the differential increase in the resistances act, therefore, in the same direction, and produce a self-accelerating physical process at the end of which C, is fully discharged. The variable resistance R,,, is, therefore, of extremely high resistance before capacitor C, could discharge. This means, in a field effect transistor, that the resistance path is blocked, and a further discharge of C, is impossible. In order to maintain the stored data, the nonlinearities of the elements and the duration of the phases must be so chosen that the residual voltage remaining at the end of the phase clock pulse at C, and at the points x and E still corresponds to a logic 1. The corresponding voltage curves of Up and U are shown in FIG. 2. During the start of a further phase clock pulse C, is again fully charged, so that the voltage curve just described starts again at the individual circuit points. Generally, the capacitances C, and C will be nonlinear. This is valid particularly if they are formed by the intrinsic capacitances of the MOS field effect transistors Q and 0, (FIGS. 8 and 9). The capacitancevoltage behavior of such capacitances which consist substantially of the input capacitance of the one transistor and a barrier layer capacitance of the other transistor is shown in FIG. 5; with p-channel MOS field effect transistors with enrichment, the capacitance drops with increasing voltage.

With regard to the voltage-time behavior at the points F and E this means that, in view of the lower voltage at F during the discharging, the capacitance is larger at this point. For discharge, it is valid that C, is larger than C With low voltages'at F, the discharge is slowed down. For this reason, the non-linearities of the capacitances and resistances must be so matched, that the voltage curves according to the diagram in FIG. 2 are obtained. The charging of the capacitor C starts more slowly than that of the capacitor C because at the start of a phase clock pulse, C is substantially greater than C,. The non-linearity of the capacitances acts, therefore, during the charging in the same direction as the non-linearity of the variable resistances, so that the voltage behavior at E and F is improved in the respect that the stored data is always retained.

FIG. 6 also shows that during a phase clock pulse the voltages at the points E and F change if the nonlinearity of the capacitances act, in accordance with FIG. 5, in the direction of the non-linearity of the variable resistances. It may be seen that, at the end of the phase clock pulse there remains between U and Up a difference U which is sufficient to provide a voltage U U also during the phase clock intervals, which is still defined as a logic 1.

The phase clock pulses can be shortened so far that the transistor Q (FIGS. 8 and 9) no longer reaches the conducting state. This is possible in view of the threshold voltages of MOS field effect transistors.

If the capacitances C and C are non-linear elements, the capacitances of which increase with rising voltage in accordance with FIG. 7, the non-linearity of the capacitances counteracts that of the variable resistances. If the effect of the capacitances is large enough, the data content of the storage element is exchanged against the negated data with every phase clock pulse. This means that after the first phase clock pulse, a logic 0 is at E, and a logic 1 at F. After the second phase clock pulse the conditions are reversed.

It is also possible to use instead of capacitances as en ergy stores, linear or non-linear inductances arranged in the discharge, charging or control branches of the variable resistors.

An additional capacitance C may be connected between the points E and F. The capacitor supports the behavior of a storage element according to the invention in so far as a stored data is retained. In this connection it should be stressed that also the diode capacitances shown in the figures at C and C support the be havior of the storage element according to the invention.

In the circuit of FIG. 8, the free main electrodes of the field effect transistors, i.e., the electrodes which are not connected to the associated diodes, are grounded, while in the circuit according to FIG. 9 these electrodes are connected in the same way as the free electrodes of the diodes with the clock generator for the phase clock pulses.

The arrangement according to the invention may be realized particularly well in integrated circuitry. Such a storage element consists, according to FIG. 10, of two MOS field effect transistors fitted into a common semiconductor body of n-type conductivity. One transistor is formed by p-type regions 2 and 3 provided at a certain distance in the semiconductor body. The channel region between these zones is covered by an insulating layer 6 which carries the control electrode 7. The other transistor consists of p-type regions 4 and 5 between which an insulating layer 6 carries a control electrode 8. The regions 3 and 4 are connected by a contact 11 to each other and to earth. The clock generator for the phase clock pulse (b is connected to the reverse contact 12 which contacts the semiconductor body 1 without barrier layer. The diode D, is formed by the barrier layer between the region 2 and the semiconductor body I; similarly, the diode D is realized by the barrier layer between the region 5 and the semiconductor body. For obtaining a circuit according to FIG. 8, the contact 9 of region 2 is connected to the control electrode 8 of the transistor Q and the contact 10 of zone 5 to the control electrode 7 of Q The contact 9 forms, therefore, the circuit point E, while the contact 10 forms the circuit point F.

In the circuit according to FIG. 9, the contact 11 may also be connected to the reverse contact 12. In this case, the reverse contact is additionally earthed through a capacitor C Naturally, the storage element according to the invention may also be realized with nchannel field effect transistors. In. this case, a logic 1 will be a positive voltage. The phase clock pulses will then also be positive voltage pulses.

It will be understood that the above description of the present invention is susceptible to various modification changes and adaptations.

What is claimed is:

1. An electric dynamically operated storage circuit consisting of a semiconductor body; two field effect transistors formed in the semiconductor body, and each having the characteristic of a variable resistance; each of said transistors having a plurality of semiconductor zones forming two main electrodes and a control electrode; means connecting one main electrode of each said transistors to said control electrode of the other of said transistors and connecting the other main electrodes of both of said transistors together to a common source; two energy stores each including a charging circuit and a discharging circuit, each of said charging circuits including a diode connected in series with the one main electrode of a respective transitor, said transistors being connected in such .a manner that their variable resistance is used by said discharge circuits; each of said diodes being formed bya barrier layer between that semiconductor zoneof its respective transitor forming the first main electrode of that transistor and the semiconductor body; a clock pulse generator connected to the region of said diodes formed by said semiconductor body so as to be connected to both of said energy stores to produce in said energy stores periodically repeating phase timing pulses, the duration of which are so selected that the stored infonnation is effected with each timing pulse.

2. A storage element as defined in claim I, wherein said energy stores include capacitances.

3. A storage element as defined in claim 2, where said capacitances are connected in parallel with said transistors.

4. A storage element as defined in claim 2, where said capacitances are connected in parallel with said diodes.

5. A storage element as defined in claim 2, wherein said capacitances comprise fixed capacitances.

6. A storage circuit as defined in claim 1, wherein said clock pulse generator applies pulses of a duration such that the stored data is renewed by each of said phase clock pulses.

7. A storage circuit as defined in claim 1, wherein said clock pulse generator applies pulses of a duration such that the stored data is exchanged with negated data at each of said phase clock pulses.

8. A storage circuit as defined in claim 1, wherein said transistors are MIS or MOS field effect transistors formed in the semiconductor body and said control electrodes are insulated from said semiconductor body.

9. A storage element as defined in claim 8, wherein said energy stores include intrinsic capacitances of the MIS or MOS field effect transistors and barrier layer capacitances of said diodes.

10. A storage element as defined in claim 1, wherein the resistance of said transistors varies with the voltage.

1 l. A storage element as defined in claim 1, wherein said variable resistors have a non-linearity and said clock pulse generator applies pulses of a length such that the variable resistance which has a low resistance value due to stored data remains lower than the resistance value of the other said variable resistance during said phase clock pulses.

12. A storage circuit as defined in claim 1, comprising in combination therewith a capacitance connected between said two first main electrodes of said transistors.

13. A storage circuit as defined in claim 1, wherein said second main electrodes are connected to ground.

14. A storage circuit as defined in claim 1, wherein said second main electrodes are connected to said clock pulse generator.

15. A storage element as defined in claim 1, wherein said energy stores include non linear inductances. 

1. An electric dynamically operated storage circuit consisting of a semiconductor body; two field effect transistors formed in the semiconductor body, and each having the characteristic of a variable resistance; each of said transistors having a plurality of semiconductor zones forming two main electrodes and a control electrode; means connecting one main electrode of each said transistors to said control electrode of the other of said transistors and connecting the other main electrodes of both of said transistors together to a common source; two energy stores each including a charging circuit and a discharging circuit, each of said charging circuits including a diode connected in series with the one main electrode of a respective transitor, said transistors being connected in such a manner that their variable resistance is used by said discharge circuits; each of said diodes being formed by a barrier layer between that semiconductor zone of its respective transitor forming the first main electrode of that transistor and the semiconductor body; a clock pulse generator connected to the region of said diodes formed by said semiconductor body so as to be connected to both of said energy stores to produce in said energy stores periodically repeating phase timing pulses, the duration of which are so selected that the stored information is effected with each timing pulse.
 2. A storage element as defined in claim 1, wherein said energy stores include capacitances.
 3. A storage element as defined in claim 2, where said capacitances are connected in parallel with said transistors.
 4. A storage element as defined in claim 2, where said capacitances are connected in parallel with said diodes.
 5. A storage element as defined in claim 2, wherein said capacitances comprise fixed capacitances.
 6. A storage circuit as defined in claim 1, wherein said clock pulse generator applies pulses of a duration such that the stored data is renewed by each of said phase clock pulses.
 7. A storage circuit as defined in claim 1, wherein said clock pulse generator applies pulses of a duration such that the stored data is exchanged with negated data at each of said phase clock pulses.
 8. A storage circuit as defined in claim 1, wherein said transistors are MIS or MOS field effect transistors formed in the semiconductor body and said control electrodes are insulated from said semiconductor body.
 9. A storage element as defined in claim 8, wherein said energy stores include intrinsic capacitances of the MIS or MOS field effect transistors and barrier layer capacitances of said diodes.
 10. A storage element as defined in claim 1, wherein the resistance of said transistors varies with the voltage.
 11. A storage element as defined in claim 1, wherein said variable resistors have a non-linearity and said clock pulse generator applies pulses of a length such that the variable resistance which has a low resistance value due to stored data remains lower than the resistance value of the other said variable resistance during said phase clock pulses.
 12. A storage circuit as defined in claim 1, comprising in combination therewith a capacitance connected between said two first main electrodes of said transistors.
 13. A storage circuit as defined in claim 1, wherein said second main electrodes Are connected to ground.
 14. A storage circuit as defined in claim 1, wherein said second main electrodes are connected to said clock pulse generator.
 15. A storage element as defined in claim 1, wherein said energy stores include non linear inductances. 